1. Field of the Invention
The present invention relates to a switch (e.g., ultra-high voltage switch), and more particularly, a switch which may include a low-threshold pass system and a level shifter (e.g., including a cascoded multi-latch architecture) for controlling the low-threshold pass system.
2. Description of the Related Art
In NAND memories, a high voltage (e.g., 20V or more) may be passed through a switch array in order to bias wordlines or other generic nodes in the array during read or modify operations. However, this may cause the devices (e.g., transistors) used in NAND memories to at times exceed the limit of a Safe Operating Area (SOA).
That is, during standard operations (read, program, erase) these devices may face voltages that could be greater than the maximum allowed voltage across gate oxide and drain-bulk or source-bulk junctions of the device, or more restrictively, along the channel (i.e., drain-source junction) of the device when the device is turned on and drains current. If this occurs, then the reliability of the entire system would be compromised or, in some cases, the device could be definitively damaged because of huge breakdown currents across the above-mentioned junctions.
Another issue that is very common for NAND memories, is related to the lack of a p-ch device with the capability of sustaining ultra-high voltages across the drain-bulk junction, source-bulk junction, and/or drain-source junction (hereinafter referred to collectively as “source/drain/bulk junctions”). Only n-ch devices with these characteristics are usually available, and these devices usually have high threshold voltage values, a parameter that is directly related to the need for sustaining very high voltages.
On the other hand, technology often offers n-ch devices capable of sustaining very high voltages across junctions, but with a threshold voltage which could be quite null or even negative, so that the devices are totally inadequate to be used as a switch.
In short, it could happen that a voltage greater than the maximum voltage allowed by the SOA of the available devices shall be dealt with during read or modify operations, and hence a very accurate architecture for switches is needed in order to manage the high voltages.
Conventionally, this is achieved in some cases with pumped switches basically made of a single stage of a charge pump.
FIG. 1 illustrates a related art pumped switch 100.
As illustrated in FIG. 1, the related art pumped switch 100 includes a transistor 110 (e.g., Pass1 transistor) that connects line L1 to line L2, and a pump device 120 which controls the transistor 110. The pump device 120 includes a pumping system 122 which receives a clock signal CLK and an enable signal ENA, and outputs a voltage Vout. The pump device 120 also includes an n-ch transistor 124 coupled to the pumping system 122, to supply voltage Vsupply and to a control node CTRL-NODE. The gate of the transistor 110 is coupled to Vout and to the gate of the n-channel transistor 124.
The n-channel transistor 124 can sustain voltages up to 30V (for instance, depending on technology) across gate oxide and drain/bulk or source/bulk junctions, and up to 15V (e.g., depending on technology) along the channel when the transistor 124 is turned on. The transistor 124 receives at one of its terminals (e.g., drain terminal) a high voltage (VSUPPLY). The clocking system is turned “on” and the gate of the transistor 124 (which has a threshold voltage Vth) is finally pumped to a voltage (VSUPPLY+Vth) which is high enough to let VSUPPLY be passed on the source side of the transistor 124 (indicated as CTRL_NODE in FIG. 1).
Thus, when the regime is reached, the voltage V(CTRL_NODE) at the source terminal of the transistor 124 is given by V(CTRL_NODE)=VSUPPLY, and the gate voltage Vout at the gate of transistor 124 is given by Vout=VSUPPLY+Vth. The gate voltage Vout of the transistor 124 is applied to the gate of the transistor 110 (e.g., pass transistor) that connects the line L1 to the line L2, activating the transistor 110 so that a short between the two lines L1, L2 is ensured and a voltage on line L1 as high as VSUPPLY can be passed on line L2.